Digital logic, in the form of integrated circuits, has found wide spread use in virtually every type of electronic system. Currently, some integrated circuits combine analog and digital devices in one package, in order to reduce the overall size of the electronic systems. The interface function is a basic function, which allows the logic of one integrated circuit device to interface with other devices within the package or outside. One important component for this interface function is the output buffer which, when enabled, provides an output which is a function of data received from other logic circuitry of the integrated circuit.
CMOS output buffers typically use a P-channel pull-up FET and a N-channel pull down FET connected to the output terminal. Depending upon the state of the data signal input, either the P-channel FET or the N-channel FET is turned on. A tri-state output buffer may be provided by turning off both the N-channel FET and the P-channel FET.
Advancement in integrated circuit technology has lead to vast improvements in the speed of integrated circuits, i.e. the time in which the output of a circuit reacts in response to a new input. Increasing integrated circuit speed has resulted in faster rise and fall times of the output voltages. Similarly, the fast rise and fall times of the output voltages have resulted in abrupt transitions of output current.
While faster speeds are very desirable, the abrupt transition of output currents creates serious problems. The package which holds an integrated circuit device has metallic leads which allow interconnection of the device to a circuit board. Each lead has a small inductance associated with it. The leads are connected to the integrated circuit using bonding wire, which also has an inductance. The time rate of change of current is governed by the equation E=L(di/dt), where L is the measure of inductance, and di/dt is the change in current with respect to time. The abrupt transition of output currents creates a large change of current at the ground and power supply leads and in the bonding wire, resulting in ground and power supply voltage spikes. These voltage spikes affect the output voltages of the device, and cause output ringing, ground bounce, and false signals.
Systems have been developed which attempt to alleviate this problem by reducing the amount of inductance L present at the leads. One method provides multiple power supply and ground leads in order to reduce the inductance L that generates the voltage spikes. However, the reduction in inductance is often insufficient to eliminate voltage spikes at the output of many devices, and may necessitate using a larger package to carry the same integrated circuit.
Another method is described by Stein et al in the U.S. Pat. No. 4,725,747, wherein change in current with respect to time (di/dt) is reduced. Stein et al. uses a plurality of CMOS complimentary pairs stages, each having a P-channel transistor and an N-channel transistor, connected by a serpentine polysilicon gate. The stages are sequentially turned on, within a delay period, in response to a changing input. The amount of delay for each stage depends on the absolute resistance of the polysilicon gate and the input capacitance of each transistor. However, since it is difficult to control the absolute resistance of the polysilicone gate in a standard CMOS process technology, the turn on delay in each stage may vary. Therefore, in designs of output buffers using this method undesirable varaition in access time may be encountered.